DeBAM: Decoder-Based Approximate Multiplier for Low Power Applications

Approximate computing is a promising method for designing power-efficient computing systems. Many image and compression algorithms are inherently error-tolerant and can allow errors up to a specific limit. In such algorithms, savings in power can be achieved by approximating the data path units, suc...

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Bibliographic Details
Published in:IEEE embedded systems letters 2021-12, Vol.13 (4), p.174-177
Main Authors: Nambi, Suresh, Kumar, U. Anil, Radhakrishnan, Kavya, Venkatesan, Mythreye, Ahmed, Syed Ershad
Format: Article
Language:English
Subjects:
Adders
Algorithms
Approximate computing
approximate multiplier
Computation
Decoding
Error analysis
Hardware
Hardware design languages
Image compression
image sharpening
Logic gates
low-power
Multipliers
Power consumption
PSNR
Sharpening
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Summary:Approximate computing is a promising method for designing power-efficient computing systems. Many image and compression algorithms are inherently error-tolerant and can allow errors up to a specific limit. In such algorithms, savings in power can be achieved by approximating the data path units, such as a multiplier. This letter presents a novel decoder logic-based multiplier design with the intent to reduce the partial products generated. Thus, leading to a reduction in the hardware complexity and power consumption while maintaining a low error rate. Our proposed design in an 8-bit format which achieves 40.96% and 22.30% power reduction compared to the accurate and approximate multipliers. Comprehensive simulations are carried out on image sharpening and compression algorithms to prove that the proposed design obtains a better quality-effort tradeoff than the existing multipliers.
ISSN:1943-0663
1943-0671
DOI:10.1109/LES.2020.3045165