A 99-mm/sup 2/, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system

A scalable single-chip 422P@ML MPEG-2 video, audio, and system encoder LSI for portable 422P@HL system is described. The encoder LSI is implemented using 0.13 /spl mu/m embedded DRAM technology. It integrates 3-M logic gates and 64-Mbit DRAM in an area of 99-mm/sup 2/. The power consumption is suppr...

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Bibliographic Details
Main Authors: Kumaki, S., Takata, H., Ajioka, Y., Ooishi, T., Ishihara, K., Hanami, A., Tsuji, T., Kanehira, Y., Watanabe, T., Morishima, C., Yoshizawa, T., Sato, H., Hattori, S., Koshio, A., Tsukamoto, K., Matsumura, T.
Format: Conference Proceeding
Language:English
Subjects:
Costs
Digital filters
Encoding
Energy consumption
HDTV
Large scale integration
Nonlinear filters
Random access memory
Real time systems
Ultra large scale integration
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Summary:A scalable single-chip 422P@ML MPEG-2 video, audio, and system encoder LSI for portable 422P@HL system is described. The encoder LSI is implemented using 0.13 /spl mu/m embedded DRAM technology. It integrates 3-M logic gates and 64-Mbit DRAM in an area of 99-mm/sup 2/. The power consumption is suppressed to 0.7-Watts by adopting a low power DRAM core. It performs real-time 422P@ML video encoding, audio encoding, and system encoding with no external DRAM. Furthermore, the encoder LSI realizes a 422P@HL video encoder with multi-chip configuration, due to its scalable architecture. This results in a PC-card size 422P@HL encoder with lowest power consumption for portable HDTV codec system.
DOI:10.1109/CICC.2001.929815