Dynamically parameterized architectures for power-aware video coding: motion estimation and DCT

• Main Authors: Burleson, W., Jain, P., Venkatraman, S.
• Format: Conference Proceeding
• Language: English
• Subjects: Circuits; Degradation; Discrete cosine transforms; Field programmable gate arrays; Motion estimation; MPEG 4 Standard; Silicon; Tiles; Video coding; Video compression
• DOI: 10.1109/DCV.2001.929936

Power-aware video coding requires a combination of high-performance and flexibility to satisfy perceptual quality requirements and meet low-power constraints. This work explores the use of dynamically configurable algorithms and architectures which leverage two fundamental properties of video processing: 1. Video content and its associated processing are highly non-uniform in both space and time. 2. Video processing can gracefully degrade in power constrained environments by exploiting perceptual tolerance. MPEG-4 has opened numerous new opportunities in both of these areas due to object-based coding techniques and algorithm feasibility. Although portable video products supporting the MPEG-4 simple profile are now available, much work remains to be done to achieve higher quality formats in a low-power environment. Much recent work has focused on low-power devices, circuits, and CAD tools, to support both general-purpose processing and more specialized processing, however it has been generally recognized that the largest gains in power efficiency come from very high-level changes to algorithms and processing systems. This work focuses on novel dynamically parameterized architectures for motion estimation (ME) and discrete cosine transform (DCT), the two most computationally intensive aspects of video coding.