High On-State Current in Chemical Vapor Deposited Monolayer MoS2 nFETs With Sn Ohmic Contacts

• Published in: IEEE electron device letters 2021-02, Vol.42 (2), p.272-275
• Main Authors: Chou, Ang-Sheng, Cheng, Chao-Ching, Liew, San-Lin, Ho, Po-Hsun, Wang, Shih-Yun, Chang, Yu-Chen, Chang, Che-Kang, Su, Yuan-Chun, Huang, Zheng-Da, Fu, Fang-Yu, Hsu, Chen-Feng, Chung, Yun-Yan, Chang, Wen-Hao, Li, Lain-Jong, Wu, Chih-I
• Format: Article
• Language: English
• Subjects: Charge carrier density; Chemical vapor deposition; Contact melting; Contact resistance; Field effect transistors; low power transistors; Melting points; Metals; Molybdenum disulfide; Monolayers; ohmic contact; Performance evaluation; re-melting phenomenon; Semiconductor devices; Silicon; Temperature measurement; Two dimensional displays
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2020.3048371

Proving the device performance and process feasibility is imperative for the realization of two-dimensional (2D) semiconductor electronics. In this work, we have successfully adopted Tin (Sn) as the Ohmic contact metal to monolayer molybdenum disulfide (MoS 2 ) grown by chemical vapor deposition (CVD) and demonstrated superior short channel n-type field effect transistor (nFET) performance reaching an ON-current of 480~\mu \text{A}/\mu \text{m} and keeping the OFF-current below 0.1 nA/ \mu \text{m} at \text{V}_{DS} = 1 V. These efforts are close to the low power specification of Si transistors in the metrics of International Roadmap for Devices and Systems (IRDS). The performance improvement could be attributed to the re-melting behavior of Sn metal. We suggest that the Sn deposited at lower temperatures could reduce the formation of interfacial defects caused by heat, and high-melting-point capping metal also could assist the re-melting phenomenon of underlying Sn contact layer. These process modifications are helpful to form smooth Sn coverage on MoS 2 , thereby reducing the contact resistance to 0.84 \text{k}\Omega \cdot \mu \text{m} . This work provides a practical pathway to form low-resistance metal contact on 2D semiconductors for performance improvement.