An 18.39 fJ/Conversion-Step 1-MS/s 12-bit SAR ADC with Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC

• Published in: IEEE access 2021-01, Vol.9, p.1-1
• Main Authors: Kuo, Hsuan-Lun, Lu, Chih-Wen, Chen, Poki
• Format: Article
• Language: English
• Subjects: Analog to digital conversion; Analog to digital converters; Analog-digital conversion; Capacitance; Capacitors; CMOS; Digital to analog conversion; Digital to analog converters; Error correction; multiple-LSB redundant CDAC; non-binary-weighted CDAC; Nonlinearity; Power demand; Quantization (signal); Redundancy; Sampling; SAR ADC; Switches
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2020.3048979

A low-power 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with split-capacitor, nonbinary-weighted, and multiple-least-significant-bit (LSB)-redundant capacitor digital-to-analog converters (CDACs) is proposed. The proposed SAR ADC with nonbinary-weighted and multiple-LSB-redundant CDACs has an optimal mechanism for correcting the bit error decisions due to noise and incomplete digital-to-analog converter (DAC) switching settling. To reduce the total capacitance, all capacitor values of the 12-bit DAC were divided by 16, and a parallel-series capacitor scheme was used to implement these noninteger capacitors. The 12-bit SAR ADC prototype was fabricated using 0.18-μm 1P6M complementary metal oxide semiconductor technology. The maximal differential nonlinearity and integral nonlinearity were measured as -0.4/0.54 and -0.81/0.89 LSB, respectively, where 1 LSB = 0.488 mV. The signal-to-noise-and-distortion ratio and effective number of bits were 69.51 dB and 11.25 bits, respectively, for the input frequency of 500 kHz and sampling rate of 1 MS/s. The proposed SAR ADC features an 18.39-fJ/conversion-step Figure-of-Merit (FoM) at the sampling rate of 1 MS/s.