MBIST Supported Multi Step Trim for Reliable eMRAM Sensing

Access Memory) has many attractive properties such as small size, fast operation speed, and good endurance. However, MRAM has a relatively small TMR (Tunneling Magnetoresistance) ratio, which means a small on-off state separation. It is a challenge to set an optimal reference resistance to reliably...

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Bibliographic Details
Main Authors: Yun, Jongsin, Nadeau-Dostie, Benoit, Keim, Martin, Schramm, Lori, Dray, Cyrille, Boujamaa, Mehdi, Gelda, Khushal
Format: Conference Proceeding
Language:English
Subjects:
Arrays
BIST
Business
Memory management
MRAM
read operation
reference trim
Resistance
Sensors
Silicon
Tunneling magnetoresistance
yield
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Summary:Access Memory) has many attractive properties such as small size, fast operation speed, and good endurance. However, MRAM has a relatively small TMR (Tunneling Magnetoresistance) ratio, which means a small on-off state separation. It is a challenge to set an optimal reference resistance to reliably differentiate "1" and "0" states. Several trimming circuits were suggested in the literature to adjust a reference value and its search range. The trim setting can be controlled manually by user input; however, it consumes huge test time and requires off-chip engineering analysis to search and apply a trim setting for an individual memory array. In this paper, we will discuss the recent silicon results of fully automated trim process leveraging existing MBIST (Memory Built-in Self-Test) resources and new features to accommodate more complicated multi-step reference setting implementation through minor update of an existing MBIST circuit. The proposed MBIST solution uses a minimal number of tests to analyze massive array properties and automatically set complicated multi-step trim settings within a chip without the need for an external tester or manual adjustments.
ISSN:2378-2250
DOI:10.1109/ITC44778.2020.9325218