Digitally Assisted Secondary Switch-and-Compare Technique for a SAR ADC

• Published in: IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2021-07, Vol.68 (7), p.2317-2321
• Main Authors: Joshi, Ashish, Shrimali, Hitesh, Sharma, Satinder Kumar
• Format: Article
• Language: English
• Subjects: AC generators; analog-to-digital converter; Calibration; Capacitors; Circuits and systems; Clocks; CMOS; comparator offset; Digital to analog converters; Energy efficiency; Logic circuits; low power and multivalent circuit; Power consumption; self-calibration; Successive approximation; supplementary LSB; Switches; Switching; System-on-chip
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2021.3053210

This brief presents a secondary switch-and-compare technique to improve the energy efficiency of a SAR ADC with minimal area and power overheads. The method exploits the self-calibrated comparator in the SAR ADC to generate a supplementary LSB. Instead of a C-DAC, this switching scheme produces voltage change required to evaluate the supplementary LSB at the calibration node of the comparator. The (N+1) ^{\text {th}} bit logic proficiently controls the secondary switching and assists the comparator in resolving the augmented LSB. A proof-of-concept (9+1)-bit 20 kS/s SAR ADC is designed in a standard 180 nm CMOS technology to demonstrate the proposed technique. The post-layout simulation results achieve energy efficiency of 51.2 fJ/conv.-step at 562 nW of average power consumption from \text{V}_{\text {DD}} of 1.8 V.