Using Schottky Barrier Diode to Improve Latch-Up Immunity for CMOS ICs Operating With Negative Voltage Sources

For some applications, the CMOS ICs need to be supplied with positive and negative voltage sources for the desired circuit operations. To supply the negative voltage source for circuit operations in the silicon chip with the common p-type substrate grounded, the isolation rings configured with n-wel...

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Bibliographic Details
Published in:IEEE electron device letters 2021-03, Vol.42 (3), p.395-397
Main Authors: Chang, Rong-Kun, Ker, Ming-Dou
Format: Article
Language:English
Subjects:
CMOS
CMOS process
Current measurement
deep n-well (DNW)
Electric potential
Electrostatic discharges
Immunity
Integrated circuits
Junctions
Latch-up
MOS devices
negative voltage supply
Pins
Schottky barrier diode (SBD)
Schottky barriers
Schottky diodes
Schottky junction
silicon-controlled rectifier (SCR)
Voltage
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Summary:For some applications, the CMOS ICs need to be supplied with positive and negative voltage sources for the desired circuit operations. To supply the negative voltage source for circuit operations in the silicon chip with the common p-type substrate grounded, the isolation rings configured with n-well (NW) and deep n-well (DNW) layers must be used to isolate the circuits of nMOS devices operating with negative voltage from the common P-substrate. Such NW/DNW isolation rings in the circuit layouts are often connected to ground (GND =0V) for the circuit operations with negative voltage source. But, a parasitic p-n-p-n path from I/O pMOS to this grounded NW/DNW isolation ring may cause the circuits at high risk to latch-up. In this letter, a novel method to improve latch-up immunity against such parasitic p-n-p-n path by using a Schottky junction is reported.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2021.3055212