A floating-body charge monitor circuit for partially depleted SOI CMOS

This paper presents a floating-body charge monitor technique, which does not require the use of body contacts. This technique improves the performance and timing robustness of MUX-type and SRAM bit line circuits on partially depleted (PD) SOI CMOS. It can also be used as a calibration tool for SOI d...

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Bibliographic Details
Main Authors: Kuang, J.B., Saccamango, M.J., Ratanaphanyarat, S.
Format: Conference Proceeding
Language:English
Subjects:
Calibration
Circuits
Latches
Mirrors
Monitoring
Partial discharges
Pulse amplifiers
Random access memory
Semiconductor device modeling
Timing
Online Access:Request full text
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Summary:This paper presents a floating-body charge monitor technique, which does not require the use of body contacts. This technique improves the performance and timing robustness of MUX-type and SRAM bit line circuits on partially depleted (PD) SOI CMOS. It can also be used as a calibration tool for SOI device models by virtue of its direct body charge monitoring.
DOI:10.1109/VLSIC.2001.934228