Strategic Reduction of Area and Power in FIR Filter Architecture for ECG Signal Acquisition

Literature on VLSI implementation of Finite Impulse Response (FIR) filters has scarce mention of dedicated filters for portable Electrocardiogram (ECG) acquisition system. Primary requirements of portable systems are compact design and low power consumption. This paper, therefore, presents design an...

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Bibliographic Details
Main Authors: Janwadkar, Sudhanshu, Dhavse, Rasika
Format: Conference Proceeding
Language:English
Subjects:
Biomedical Signal Processing
Carry Save Adder
Computer architecture
Electrocardiogram
Electrocardiography
Field programmable gate arrays
Finite impulse response filters
FIR Filter
Power demand
Quantization (signal)
Systematics
Vedic FIR filter
Vedic Multiplier
VLSI
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Summary:Literature on VLSI implementation of Finite Impulse Response (FIR) filters has scarce mention of dedicated filters for portable Electrocardiogram (ECG) acquisition system. Primary requirements of portable systems are compact design and low power consumption. This paper, therefore, presents design and implementation of low-area and low-power FIR filter architecture for removing high-frequency noise from ECG. We propose a systematic LSBs quantization approach to lower the area-power complexity of Urdhva-Tiryagbhyam sutra based Vedic Multiplier. Vedic FIR filter of order L = 16, 32 and 64, are constructed using this optimized 16X16 Vedic Multiplier. The filter architecture is described in VHDL language and implemented on Artix-7 FPGA xc7a200tfbg676-2 using Xilinx Vivado 2019.2 Design Suite. Comparison of proposed architecture with state of the art FIR filters in literature reveals 52.07% reduction in slices and 69.63% reduction in power consumption. The quantization costs meager 0.135 mV 2 Mean Square Error(MSE) against uncontaminated ECG.
ISSN:2325-9418
DOI:10.1109/INDICON49873.2020.9342386