A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage

This article presents a 1.2-V, 1.8-Gb/s/pin 16-Tb NAND flash memory multi-chip package incorporating 16 dies of 1-Tb NAND flash memory and the third-generation F-chip. The proposed third-generation F-chip is developed to meet the performance requirements of a high-capacity storage device that adopts...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2021-04, Vol.56 (4), p.1129-1140
Main Authors: Na, Daehoon, Lee, Jang-woo, Lee, Seon-Kyoo, Cho, Hwasuk, Lee, Junha, Yang, Manjae, Song, Eunjin, Kavala, Anil, Kim, Tongsung, Jang, Dong-Su, Jo, Youngmin, Shin, Ji-Yeon, Chun, Byung-Kwan, Lee, Tae-sung, Jeong, Byunghoon, Yoon, Chi-Weon, Kang, Dongku, Lee, Seungjae, Ihm, Jungdon, Byeon, Dae Seok, Lee, Jinyub, Song, Jai Hyuk
Format: Article
Language:English
Subjects:
Bonding
Built-in self-test
Built-in self-test (BIST)
channel loading
Chips (memory devices)
Clocks
dual bi-directional buffer
F-chip
Flash memory (computers)
in-package buffer chip
in-package training
Loading
Locking
multi-chip training
Power consumption
re-training decision
Self tests
Signal integrity
Solid state devices
time-to-digital converter (TDC)-based delay-locked loop (DLL)
Topology
Training
Wires
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Summary:This article presents a 1.2-V, 1.8-Gb/s/pin 16-Tb NAND flash memory multi-chip package incorporating 16 dies of 1-Tb NAND flash memory and the third-generation F-chip. The proposed third-generation F-chip is developed to meet the performance requirements of a high-capacity storage device that adopts a PCIe Gen four-host interface for higher data throughput. It is implemented with dual bi-directional transceiver architecture and signal retiming scheme to maximize the valid data window opening on solid-state drive (SSD) channels. Also, it facilitates training between F-chip and NAND using an on-chip delay-locked loop whose locking is proposed in strobe-based NAND systems to achieve sufficient signal integrity (SI) of the in-package channel at a speed of 1.8 Gb/s/pin. Embedded built-in self-test evaluates un-selected paths and determines if re-training is required without losing data throughput performance. This work achieves a 35% improvement in the I/O operational speed performance and a 23% reduction in the I/O power consumption in comparison with the previous generations.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2021.3052492