Highly scalable sub-10F/sup 2/ 1T1C COB cell for high density FRAM

Recently, technology innovation for high density and high performance FRAM has been pronounced. Among the breakthrough technologies for high density and high performance FRAM, 1T1C capacitor-on-bitline (COB) cell technology is essential because it can greatly reduce FRAM cell size compared to previo...

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Main Authors: Lee, S.Y., Kim, H.H., Jung, D.J., Song, Y.J., Jang, N.W., Choi, M.K., Jeon, B.K., Lee, Y.T., Lee, K.M., Joo, S.H., Park, S.O., Kim, K.
Format: Conference Proceeding
Language:English
Subjects:
Electrodes
Etching
Ferroelectric films
Ferroelectric materials
MIM capacitors
Nonvolatile memory
Oxidation
Plugs
Random access memory
Tin
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Summary:Recently, technology innovation for high density and high performance FRAM has been pronounced. Among the breakthrough technologies for high density and high performance FRAM, 1T1C capacitor-on-bitline (COB) cell technology is essential because it can greatly reduce FRAM cell size compared to previous and current 2T2C FRAMs (Kinam Kim, 1999; Lee et al., 1999). Design improvement for enhanced sensing ability is also a promising technology for highly reliable mega-bit density FRAM (Jeon et al, 2000). Although the recent demonstration shows a promising future for stand-alone FRAM applications, current 1T1C COB FRAM still has incomparably large cell size factor compared to DRAM and flash. This is one of the most challenging issues that FRAM faces for developing high-density stand-alone memory. In this work, a novel cell structure for sub-10 F/sup 2/ cell size is for the first time developed. The key technologies for the sub-10 F/sup 2/ novel cell are: (1) advanced oxidation barrier and PZT film technologies which enables MIM ferroelectric capacitors to be lowered to /spl sim/500 nm thick stack: (2) single-mask capacitor etching technology which can produce >80/spl deg/ ferroelectric capacitor fence slope; (3) no cell via contact technology by which capacitor pitch can ideally be reduced to 2F; (4) an Al-reflow process which enables sub-0.4 /spl mu/m back-end interconnection without degrading the ferroelectric capacitor. The novel cell is demonstrated with an experimental 4 Mb FRAM, where the 1T1C COB cell is fabricated with folded bit line architecture and plate line-up sensing scheme.
DOI:10.1109/VLSIT.2001.934974