DRAM scaling-down to 0.1 /spl mu/m generation using bitline spacerless storage node SAC and RIR capacitor with TiN contact plug

As DRAM downscaling approaches the 0.1 /spl mu/m generation, problems related to transistor short channel effects, storage capacitance, gap filling of high aspect ratio patterns, and leakage currents through each module must be solved. Among these, processing around the storage node self-aligned con...

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Bibliographic Details
Main Authors: Beom-Jun Jin, Young-Pil Kim, Byeong-Yun Nam, Hyoung-Joon Kim, Young-Wook Park, Joo-Tae Moon
Format: Conference Proceeding
Language:English
Subjects:
Capacitors
Contact resistance
Etching
Filling
Insulation
Leakage current
Material storage
Plugs
Random access memory
Tin
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Summary:As DRAM downscaling approaches the 0.1 /spl mu/m generation, problems related to transistor short channel effects, storage capacitance, gap filling of high aspect ratio patterns, and leakage currents through each module must be solved. Among these, processing around the storage node self-aligned contact (SAC) is the most critical problem for integration of capacitor-on-bitline (COB) DRAM devices because it is one of the deepest contacts with high aspect ratio; and it reaches the cell transistor junction. However, few reports have addressed this issue, while others have been reported elsewhere (Song et al., 2000; Jeong et al., 2000; Won et al., 2000; Kim et al., 2000). In this paper, a novel process of bitline spacerless storage node SAC and Ru-Ta/sub 2/O/sub 5/-Ru (RIR) capacitor with TiN contact plug is studied for the integration of 0.1 /spl mu/m design-rule based DRAMs. It was found that the spacerless SAC process made downscaling to the 0.1 /spl mu/m design-rule possible and also that it has better electrical properties than the conventional SAC.
DOI:10.1109/VLSIT.2001.934982