A Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for Core-to-Core Links

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2021-05, Vol.29 (5), p.883-894
• Main Authors: Yang, Ching-Yuan, Li, Miao-Shan, Chuang, Ai-Jia
• Format: Article
• Language: English
• Subjects: Bidirectional interconnection; Circuits; clock synchronization; clock-deskewing circuit (CDC); Clocks; CMOS; Compensation; Delay lines; delay-locked loop (DLL); Delays; dual locking loops; Integrated circuit interconnections; Locking; low-voltage differential signal (LVDS) input/outputs (IOs); Synchronization; Topology; Vibration; voltage-controlled delay line (VCDL); wide range; Wires
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2021.3056506

Without any dummy element for phase compensation, a clock-deskewing circuit (CDC) using a master-slave delay-locked loop (MSDLL) configuration is presented to synchronize the clocks for cascaded core-to-core links. The dual-locking CDC provides mismatch-insensitive compensation of interconnected wires, input/outputs (IOs), and clock buffers. The MSDLL incorporates the digital-selection folded coarse-fine voltage-controlled delay line (FCF-VCDL) to provide a wide range operations. The proposed FCF-VCDL scheme is constructed from the combination of positive and negative gains of different VCDLs. In addition, a power-controlled regime is employed in the FCF-VCDL to adaptively lower the power dissipation. Implemented with 0.18- \mu \text{m} CMOS, the CDC can provide 20 MHz to 2 GHz with the help of FCF-VCDLs. The 2-GHz clock jitter is 6.78 ps (pk-pk), and the total power dissipation is 20 mW under a 1.8-V supply.