SPAD FDSOI cell optimization for lower dark count rate achievement

This article presents an optimization of Single Photon Avalanche Diodes (SPAD) implemented in CMOS 28nm Fully Depleted Silicon-On- Insulator technology. With the standard process and design rules, first attempt of SPAD cells exhibited high Dark Count Rate (DCR) at low excess voltage, attributed main...

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Bibliographic Details
Main Authors: Issartel, D., de Albuquerque, T. Chaves, Clerc, R., Pittet, P., Cellier, R., Golanski, D., Cathelin, A., Calmon, F.
Format: Conference Proceeding
Language:English
Subjects:
CMOS FDSOI
Dark Count Rate
Layout
Optimization
Silicon
Silicon-on-insulator
Single-photon avalanche diodes
SPAD
TCAD Simulation
Tunneling
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Summary:This article presents an optimization of Single Photon Avalanche Diodes (SPAD) implemented in CMOS 28nm Fully Depleted Silicon-On- Insulator technology. With the standard process and design rules, first attempt of SPAD cells exhibited high Dark Count Rate (DCR) at low excess voltage, attributed mainly to band-to-band mechanism associated with field-enhanced trap assisted tunneling effects. In this study, we propose the modification of the diode junction profile to increase the breakdown voltage, as well as the modification of the SPAD architecture (Shallow Trench Isolation, STI layout). The obtained results with the optimized SPAD confirm significant lower DCR achievement allowing higher excess bias voltages.
ISSN:2472-9132
DOI:10.1109/EUROSOI-ULIS49407.2020.9365292