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SPAD FDSOI cell optimization for lower dark count rate achievement
This article presents an optimization of Single Photon Avalanche Diodes (SPAD) implemented in CMOS 28nm Fully Depleted Silicon-On- Insulator technology. With the standard process and design rules, first attempt of SPAD cells exhibited high Dark Count Rate (DCR) at low excess voltage, attributed main...
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| creator | Issartel, D. de Albuquerque, T. Chaves Clerc, R. Pittet, P. Cellier, R. Golanski, D. Cathelin, A. Calmon, F. |
| description | This article presents an optimization of Single Photon Avalanche Diodes (SPAD) implemented in CMOS 28nm Fully Depleted Silicon-On- Insulator technology. With the standard process and design rules, first attempt of SPAD cells exhibited high Dark Count Rate (DCR) at low excess voltage, attributed mainly to band-to-band mechanism associated with field-enhanced trap assisted tunneling effects. In this study, we propose the modification of the diode junction profile to increase the breakdown voltage, as well as the modification of the SPAD architecture (Shallow Trench Isolation, STI layout). The obtained results with the optimized SPAD confirm significant lower DCR achievement allowing higher excess bias voltages. |
| doi_str_mv | 10.1109/EUROSOI-ULIS49407.2020.9365292 |
| format | conference_proceeding |
| fullrecord | <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_9365292</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>9365292</ieee_id><sourcerecordid>9365292</sourcerecordid><originalsourceid>FETCH-LOGICAL-h237t-99fd9be3da9bf4ed790c37f499a84176032afc53728782eeee55c4c89025b5403</originalsourceid><addsrcrecordid>eNotj0tLxDAYRaMgOIz9BW6yctcxzybfcpyXhULF2vWQpikT7WNIq6K_3oJzN2dx4XAvQg-UrCgl8LgrX_MiT-MySwsBgqgVI4ysgCeSAbtCEShNFdNUq0TKa7RgQrEYKGe3KBrHd0IITWjCtVqgp-JlvcX77ezD1rUtHs6T7_yvmfzQ42YIuB2-XcC1CR_YDp_9hIOZHDb25N2X61w_3aGbxrSjiy5conK_e9s8x1l-SDfrLD4xrqYYoKmhcrw2UDXC1QqI5aoRAEYLqhLCmWms5PNwpZmbI6UVVgNhspKC8CW6__f6uTueg-9M-DleXvM_bpxNhg</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>SPAD FDSOI cell optimization for lower dark count rate achievement</title><source>IEEE Xplore All Conference Series</source><creator>Issartel, D. ; de Albuquerque, T. Chaves ; Clerc, R. ; Pittet, P. ; Cellier, R. ; Golanski, D. ; Cathelin, A. ; Calmon, F.</creator><creatorcontrib>Issartel, D. ; de Albuquerque, T. Chaves ; Clerc, R. ; Pittet, P. ; Cellier, R. ; Golanski, D. ; Cathelin, A. ; Calmon, F.</creatorcontrib><description>This article presents an optimization of Single Photon Avalanche Diodes (SPAD) implemented in CMOS 28nm Fully Depleted Silicon-On- Insulator technology. With the standard process and design rules, first attempt of SPAD cells exhibited high Dark Count Rate (DCR) at low excess voltage, attributed mainly to band-to-band mechanism associated with field-enhanced trap assisted tunneling effects. In this study, we propose the modification of the diode junction profile to increase the breakdown voltage, as well as the modification of the SPAD architecture (Shallow Trench Isolation, STI layout). The obtained results with the optimized SPAD confirm significant lower DCR achievement allowing higher excess bias voltages.</description><identifier>EISSN: 2472-9132</identifier><identifier>EISBN: 9781728187655</identifier><identifier>EISBN: 1728187656</identifier><identifier>DOI: 10.1109/EUROSOI-ULIS49407.2020.9365292</identifier><language>eng</language><publisher>IEEE</publisher><subject>CMOS FDSOI ; Dark Count Rate ; Layout ; Optimization ; Silicon ; Silicon-on-insulator ; Single-photon avalanche diodes ; SPAD ; TCAD Simulation ; Tunneling</subject><ispartof>2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2020, p.1-5</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9365292$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,27925,54555,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9365292$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Issartel, D.</creatorcontrib><creatorcontrib>de Albuquerque, T. Chaves</creatorcontrib><creatorcontrib>Clerc, R.</creatorcontrib><creatorcontrib>Pittet, P.</creatorcontrib><creatorcontrib>Cellier, R.</creatorcontrib><creatorcontrib>Golanski, D.</creatorcontrib><creatorcontrib>Cathelin, A.</creatorcontrib><creatorcontrib>Calmon, F.</creatorcontrib><title>SPAD FDSOI cell optimization for lower dark count rate achievement</title><title>2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)</title><addtitle>EUROSOI-ULIS</addtitle><description>This article presents an optimization of Single Photon Avalanche Diodes (SPAD) implemented in CMOS 28nm Fully Depleted Silicon-On- Insulator technology. With the standard process and design rules, first attempt of SPAD cells exhibited high Dark Count Rate (DCR) at low excess voltage, attributed mainly to band-to-band mechanism associated with field-enhanced trap assisted tunneling effects. In this study, we propose the modification of the diode junction profile to increase the breakdown voltage, as well as the modification of the SPAD architecture (Shallow Trench Isolation, STI layout). The obtained results with the optimized SPAD confirm significant lower DCR achievement allowing higher excess bias voltages.</description><subject>CMOS FDSOI</subject><subject>Dark Count Rate</subject><subject>Layout</subject><subject>Optimization</subject><subject>Silicon</subject><subject>Silicon-on-insulator</subject><subject>Single-photon avalanche diodes</subject><subject>SPAD</subject><subject>TCAD Simulation</subject><subject>Tunneling</subject><issn>2472-9132</issn><isbn>9781728187655</isbn><isbn>1728187656</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2020</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotj0tLxDAYRaMgOIz9BW6yctcxzybfcpyXhULF2vWQpikT7WNIq6K_3oJzN2dx4XAvQg-UrCgl8LgrX_MiT-MySwsBgqgVI4ysgCeSAbtCEShNFdNUq0TKa7RgQrEYKGe3KBrHd0IITWjCtVqgp-JlvcX77ezD1rUtHs6T7_yvmfzQ42YIuB2-XcC1CR_YDp_9hIOZHDb25N2X61w_3aGbxrSjiy5conK_e9s8x1l-SDfrLD4xrqYYoKmhcrw2UDXC1QqI5aoRAEYLqhLCmWms5PNwpZmbI6UVVgNhspKC8CW6__f6uTueg-9M-DleXvM_bpxNhg</recordid><startdate>20200901</startdate><enddate>20200901</enddate><creator>Issartel, D.</creator><creator>de Albuquerque, T. Chaves</creator><creator>Clerc, R.</creator><creator>Pittet, P.</creator><creator>Cellier, R.</creator><creator>Golanski, D.</creator><creator>Cathelin, A.</creator><creator>Calmon, F.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>20200901</creationdate><title>SPAD FDSOI cell optimization for lower dark count rate achievement</title><author>Issartel, D. ; de Albuquerque, T. Chaves ; Clerc, R. ; Pittet, P. ; Cellier, R. ; Golanski, D. ; Cathelin, A. ; Calmon, F.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-h237t-99fd9be3da9bf4ed790c37f499a84176032afc53728782eeee55c4c89025b5403</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2020</creationdate><topic>CMOS FDSOI</topic><topic>Dark Count Rate</topic><topic>Layout</topic><topic>Optimization</topic><topic>Silicon</topic><topic>Silicon-on-insulator</topic><topic>Single-photon avalanche diodes</topic><topic>SPAD</topic><topic>TCAD Simulation</topic><topic>Tunneling</topic><toplevel>online_resources</toplevel><creatorcontrib>Issartel, D.</creatorcontrib><creatorcontrib>de Albuquerque, T. Chaves</creatorcontrib><creatorcontrib>Clerc, R.</creatorcontrib><creatorcontrib>Pittet, P.</creatorcontrib><creatorcontrib>Cellier, R.</creatorcontrib><creatorcontrib>Golanski, D.</creatorcontrib><creatorcontrib>Cathelin, A.</creatorcontrib><creatorcontrib>Calmon, F.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library Online</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Issartel, D.</au><au>de Albuquerque, T. Chaves</au><au>Clerc, R.</au><au>Pittet, P.</au><au>Cellier, R.</au><au>Golanski, D.</au><au>Cathelin, A.</au><au>Calmon, F.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>SPAD FDSOI cell optimization for lower dark count rate achievement</atitle><btitle>2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)</btitle><stitle>EUROSOI-ULIS</stitle><date>2020-09-01</date><risdate>2020</risdate><spage>1</spage><epage>5</epage><pages>1-5</pages><eissn>2472-9132</eissn><eisbn>9781728187655</eisbn><eisbn>1728187656</eisbn><abstract>This article presents an optimization of Single Photon Avalanche Diodes (SPAD) implemented in CMOS 28nm Fully Depleted Silicon-On- Insulator technology. With the standard process and design rules, first attempt of SPAD cells exhibited high Dark Count Rate (DCR) at low excess voltage, attributed mainly to band-to-band mechanism associated with field-enhanced trap assisted tunneling effects. In this study, we propose the modification of the diode junction profile to increase the breakdown voltage, as well as the modification of the SPAD architecture (Shallow Trench Isolation, STI layout). The obtained results with the optimized SPAD confirm significant lower DCR achievement allowing higher excess bias voltages.</abstract><pub>IEEE</pub><doi>10.1109/EUROSOI-ULIS49407.2020.9365292</doi><tpages>5</tpages></addata></record> |
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| identifier | EISSN: 2472-9132 |
| ispartof | 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2020, p.1-5 |
| issn | 2472-9132 |
| language | eng |
| recordid | cdi_ieee_primary_9365292 |
| source | IEEE Xplore All Conference Series |
| subjects | CMOS FDSOI Dark Count Rate Layout Optimization Silicon Silicon-on-insulator Single-photon avalanche diodes SPAD TCAD Simulation Tunneling |
| title | SPAD FDSOI cell optimization for lower dark count rate achievement |
| url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-21T03%3A43%3A05IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=SPAD%20FDSOI%20cell%20optimization%20for%20lower%20dark%20count%20rate%20achievement&rft.btitle=2020%20Joint%20International%20EUROSOI%20Workshop%20and%20International%20Conference%20on%20Ultimate%20Integration%20on%20Silicon%20(EUROSOI-ULIS)&rft.au=Issartel,%20D.&rft.date=2020-09-01&rft.spage=1&rft.epage=5&rft.pages=1-5&rft.eissn=2472-9132&rft_id=info:doi/10.1109/EUROSOI-ULIS49407.2020.9365292&rft.eisbn=9781728187655&rft.eisbn_list=1728187656&rft_dat=%3Cieee_CHZPO%3E9365292%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-h237t-99fd9be3da9bf4ed790c37f499a84176032afc53728782eeee55c4c89025b5403%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=9365292&rfr_iscdi=true |