4.8 An Area and Energy Efficient 0.12nJ/Pixel 8K 30fps AV1 Video Decoder in 5nm CMOS Process

Major content providers such as YouTube and Netflix use AV1, a state-of-art video coding standard that was finalized in 2018. This paper presents a video processor that supports the AV1 standard via a Multi-Format video Decoder (MFD). An MFD can decode various video coding standards, such as H.264/A...

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Bibliographic Details
Main Authors: Kim, Tae Sung, Lee, Seokhyun, Lee, Kyungkoo, Shin, Sunyoung, Jun, SeungSick, Lee, YongMi, Lee, Seungyong, Kang, Homin, Yim, Changhyun, Lim, Yohan, Moon, Eikyung, Lim, Sukhwan, Jeong, Kyungah, Kang, Inyup
Format: Conference Proceeding
Language:English
Subjects:
CMOS process
Decoding
Logic gates
Random access memory
Solid state circuits
UHDTV
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Summary:Major content providers such as YouTube and Netflix use AV1, a state-of-art video coding standard that was finalized in 2018. This paper presents a video processor that supports the AV1 standard via a Multi-Format video Decoder (MFD). An MFD can decode various video coding standards, such as H.264/AVC, HEVC and AV1. The video decoder can decode up to 8K Ultra HD (8K-UHD) video at 30fps at 468MHz core clock frequency. The MFD is fabricated using a state-of-the-art 5nm CMOS process with a 5,835k NAND2 equivalent gate count and 518kB SRAM. For AV1, MFD dissipates 116mW for decoding AV1 7680 \times4320p video at 30fps (0.12nJ/pixel) with core operating voltage at 0.7V.
ISSN:2376-8606
DOI:10.1109/ISSCC42613.2021.9366011