Introducing 2D-FETs in Device Scaling Roadmap using DTCO

Superior electrostatic control of 2D-FETs enables continued logic power-performance-area (PPA) scaling beyond the 2nm node. Here, we show that WS 2 -based 2D devices give ~40% inverter performance boost against Si at imec 2nm node, using a process-aware DTCO approach. The DTCO is conducted based on...

Full description

Saved in:
Bibliographic Details
Main Authors: Ahmed, Z., Afzalian, A., Schram, T., Jang, D., Verreck, D., Smets, Q., Schuddinck, P., Chehab, B., Sutar, S., Arutchelvan, G., Soussou, A., Asselberghs, I., Spessot, A., Radu, I. P., Parvais, B., Ryckaert, J., Na, M. H.
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
Data models
Logic gates
Mathematical model
Schottky barriers
Silicon
Two dimensional displays
Citations: Items that cite this one
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Superior electrostatic control of 2D-FETs enables continued logic power-performance-area (PPA) scaling beyond the 2nm node. Here, we show that WS 2 -based 2D devices give ~40% inverter performance boost against Si at imec 2nm node, using a process-aware DTCO approach. The DTCO is conducted based on an ab-initio calibrated, physical compact model while area scaling is based on contacted gate pitch scaling. Side contacted source/drain, vertically-stacked 2D sheets and fork-sheet architecture are highlighted as key enablers of 2D-FET technology for multiple advanced nodes, using experimentally realistic mobility and Schottky barrier height conditions.
ISSN:2156-017X
DOI:10.1109/IEDM13553.2020.9371906