Performance-Power Management Aware State-of - the-Art 5nm FinFET Design(5LPE) with Dual CPP from Mobile to HPC Application

In this paper, we demonstrate state of the art 5nm technology (5LPE) having co-optimization process for Dual CPP (Critical Poly-Pitch) technology to maximize Product Power-Performance-Area by separating both high speed and low power blocks. As a result, 5LPE successfully has 10% speed gain or 20% po...

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Bibliographic Details
Main Authors: Jeong, Jaehun, Ko, Young Gun, Son, Kihwang, Kim, Sung Won, Youn Kim, Ju, Choi, Jeongmin, Lee, Hyungjong, Lee, Ho, Lee, Sihyung, Shin, Chunghwan, Hong, Heebum, Jo, Sung-il, Lee, Youngho, Choi, Byungha, Kim, Jaechul, Lee, Minseong, Jung, Kyunghoon, Yasuda-Masuoka, Yuri, Youn, Jong Mil, Jeong, Gitae
Format: Conference Proceeding
Language:English
Subjects:
FinFETs
Fingers
Loading
Optimization
Performance evaluation
Resistance
Transistors
Online Access:Request full text
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Summary:In this paper, we demonstrate state of the art 5nm technology (5LPE) having co-optimization process for Dual CPP (Critical Poly-Pitch) technology to maximize Product Power-Performance-Area by separating both high speed and low power blocks. As a result, 5LPE successfully has 10% speed gain or 20% power gain and 0.75× logic area over our previous 7nm technology [1] with more advanced FinFET technology having EUV process and design optimization.
ISSN:2156-017X
DOI:10.1109/IEDM13553.2020.9371958