3D Integration of Vertical-Stacking of MoS2 and Si CMOS Featuring Embedded 2T1R Configuration Demonstrated on Full Wafers

For the first time, a 3D stacking of MoS 2 and Si CMOS integrated with embedded RRAM is proposed and fabricated, and CMOS inverter comprised of MoS 2 nFET and Si pFET is demonstrated. Vertically stacked multiple MoS 2 channels are required for the performance matching. Resistive switching (RS) of a...

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Main Authors: Su, C. J., Huang, M. K., Lee, K. S., Hu, V. P. H., Huang, Y. F., Zheng, B. C., Yao, C. H., Lin, N. C., Kao, K. H., Hong, T. C., Sung, P. J., Wu, C. T., Yu, T. Y., Lin, K. L., Tseng, Y. C., Lin, C. L., Lee, Y. J., Chao, T. S., Li, J. Y., Wu, W. F., Shieh, J. M., Wang, Y. H., Yeh, W. K.
Format: Conference Proceeding
Language:English
Subjects:
Field effect transistors
Molybdenum
Silicon
Stacking
Sulfur
Surface treatment
Three-dimensional displays
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Summary:For the first time, a 3D stacking of MoS 2 and Si CMOS integrated with embedded RRAM is proposed and fabricated, and CMOS inverter comprised of MoS 2 nFET and Si pFET is demonstrated. Vertically stacked multiple MoS 2 channels are required for the performance matching. Resistive switching (RS) of a Ti/MoS 2 /p + -Si structure showing high ON/OFF ratio of 10 6 is demonstrated firstly by highly Si-compatible process. Surface modification is the key to formation of uniform and smooth stacked MoS 2 multiple channels and to enhanced resistive switching endurance. This scheme can be applied to CMOS-based bipolar RRAM 1T1R or 2T1R without increasing the cell size. Our work offers a new pathway with high feasibility of integrated 2D materials and Si FETs into CMOS to enabling 3D embedded logics and memories for future computing systems.
ISSN:2156-017X
DOI:10.1109/IEDM13553.2020.9371988