First Demonstration of heterogenous Complementary FETs utilizing Low-Temperature (200 °C) Hetero-Layers Bonding Technique (LT-HBT)

• Main Authors: Hong, T.-Z., Chang, W.-H., Agarwal, A., Huang, Y.-T., Yang, C.-Y., Chu, T.-Y., Chao, H.-Y., Chuang, Y., Chung, S.-T., Lin, J.-H., Luo, S.-M., Tsai, C.-J., Li, M.-J., Yu, X.-R., Lin, N.-C., Cho, T.-C., Sung, P.-J., Su, C.-J., Luo, G.-L., Hsueh, F.-K., Lin, K.-L., Ishii, H., Irisawa, T., Maeda, T., Wu, C.-T., Ma, W. C.-Y., Lu, D.-D., Kao, K.-H., Lee, Y.-J., Chen, H. J.-H., Lin, C.-L., Chuang, R. W., Huang, K.-P., Samukawa, S., Li, Y.-M., Tarng, J.-H., Chao, T.-S., Miura, M., Huang, G.-W., Wu, W.-F., Li, J.-Y., Shieh, J.-M., Wang, Y.-H., Yeh, W.-K.
• Format: Conference Proceeding
• Language: English
• Subjects: Bonding; Field effect transistors; Germanium; Silicon; Substrates; Thermal stability; Three-dimensional displays
• ISSN: 2156-017X
• DOI: 10.1109/IEDM13553.2020.9372001

For the first time, we demonstrate heterogeneous complementary FETs (hCFETs) with Ge and Si channels fabricated with a layer transfer technique. The 3D channel stacking integration particularly employs a low-temperature (200 °C) hetero-layers bonding technique (LT-HBT) realized by a surface activating chemical treatment at room temperature, enabling Ge channels bonded onto Si wafers. Furthermore, to obtain symmetric performance in n/p FETs, a multi-channel structure of two-channel Si and one-channel Ge is also implemented. Wafer-scale LT-HBT is demonstrated successfully, showing new opportunities for the ultimate device footprint scaling with heterogeneous integration.