Multi Voltage High Performance Bidirectional Buffer in a Low Voltage CMOS process

The fundamental challenge in designing high performance input/output circuits stems from interface voltages not scaling at the same rate as the microprocessor core voltages. This typically translates to designing multi-voltage interface circuits with single lower voltage gate oxide components to red...

Full description

Saved in:
Bibliographic Details
Main Authors: Kalra, Pranshu, Rajagopal, Devraj, Seth, Sumantra, Sirohi, Anshul
Format: Conference Proceeding
Language:English
Subjects:
Channel Hot Carrier
DENMOS
DEPMOS
Driver
Gate Oxide Integrity
Hot carriers
Input buffer
Integrated circuit reliability
Logic gates
Low voltage
Output buffer
Performance evaluation
Receiver
Topology
Transmitter
Voltage control
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The fundamental challenge in designing high performance input/output circuits stems from interface voltages not scaling at the same rate as the microprocessor core voltages. This typically translates to designing multi-voltage interface circuits with single lower voltage gate oxide components to reduce mask cost. While numerous topologies exist to overcome the associated gate oxide reliability challenges, they invariably run into bottlenecks when targeted for high performance. In this paper, a multi-voltage bidirectional buffer built using just 1.8V transistors in a 65nm process is presented. Proposed solution includes two novel schemes consisting of (1) a replica driver based pre-driver compensation scheme for output buffer, and (2) a new reduced crowbar contention based low skew input buffer. These circuits in conjunction not only help achieve 200MHz operational frequency, but also do so with competitive area while eliminating gate oxide and channel hot carrier associated reliability constraints.
ISSN:2158-1525
2158-1525
DOI:10.1109/ISCAS51556.2021.9401204