An 8.1 ENOB 10bit 400MS/s Pipelined ADC Using SAR and Sub-Ranging Flash

• Main Authors: Kwon, Yigi, Min, Byounghan, Lee, Jinhwan, Lee, Wooyol, Yang, Sunghyun
• Format: Conference Proceeding
• Language: English
• Subjects: Analog-to-Digital Converter; Asynchronous Successive Approximation Register (SAR) ADC; CMOS process; Comparator Offset Calibration; Flash ADC using Sub-ranging scheme; Pipelined SAR ADC; Pipelines; Power demand; Prototypes; Registers; System-on-chip; Timing
• ISSN: 2158-1525; 2158-1525
• DOI: 10.1109/ISCAS51556.2021.9401263

This paper proposes a pipeline ADC consisting of a first stage SAR ADC and a second stage Flash ADC. This ADC has a 10-bit resolution at 0.9 V power supply voltage and operates at 400 MS/s. The first stage SAR ADC is 6bit resolution, operates in an asynchronous type, and calibrates the offset of the internal comparator before normal operation of the ADC. The second stage Flash ADC outputs 5 bit digital outputs, and a sub-ranging scheme is used to reduce the number of pre-amplifier required. This prototype ADC is manufactured using 28nm CMOS process and consumes 4.55mW power at 400MS/s operation at 0.9V supply voltage, and the chip area is 0.011mm 2 . The SNDR of 50.5 dB at input frequency 1 MHz, the SNDR of 45.2 dB at 100 MHz input was obtained.