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TPDICE and Sim Based 4-Node-Upset Completely Hardened Latch Design for Highly Robust Computing in Harsh Radiation
Technology scaling and charge-sharing make nano- scale CMOS latches become severely vulnerable to multiple-node upsets (MNUs). This paper proposes a triple-path dual- interlocked-storage-cell (TPDICE) and soft-error interceptive module (SIM) based 4-Node-Upset (4NU) completely hardened latch, namely...
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Main Authors: | , , , , , , , |
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Format: | Conference Proceeding |
Language: | English |
Subjects: | |
Online Access: | Request full text |
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Summary: | Technology scaling and charge-sharing make nano- scale CMOS latches become severely vulnerable to multiple-node upsets (MNUs). This paper proposes a triple-path dual- interlocked-storage-cell (TPDICE) and soft-error interceptive module (SIM) based 4-Node-Upset (4NU) completely hardened latch, namely 4NUHL latch, that can completely tolerate soft errors, such as 4NUs. The latch mainly consists of 2 TPDICEs and a 3-level SIM which comprises six 2-input C-elements. Owing to the single-node-upset self-recoverability and multiple storage nodes of TPDICEs and the soft-error interception capability of the SIM, the latch can provide complete 4NU tolerance. Simulation results demonstrate that the proposed 4NUHL latch is completely 4NU hardened. Furthermore, we use a high-speed path, clock-gating, and a few transistors to reduce overhead of the proposed latch. We compared the proposed latch with state-of- the-art hardened latches in terms of reliability and overhead to demonstrate the advantages of the proposed latch. |
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ISSN: | 2158-1525 2158-1525 |
DOI: | 10.1109/ISCAS51556.2021.9401453 |