Frequency, LET, and Supply Voltage Dependence of Logic Soft Errors at the 7-nm Node

Logic soft-error rates are expected to exceed latch soft-error rates at advanced technology nodes due to operating frequencies in the GHz range. Predictive models for logic soft-errors need difficult-to-obtain data for single-event transient pulse widths. This work proposes an empirical method for e...

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Bibliographic Details
Main Authors: Xiong, Y., Feeley, A., Massengill, L.W., Bhuva, B.L., Wen, S.-J., Fung, R.
Format: Conference Proceeding
Language:English
Subjects:
FinFET Technology
Latches
Logic circuits
Logic Single Event Errors
Predictive models
Reliability engineering
Shift registers
Single Event Upset
Transient analysis
Transistors
Online Access:Request full text
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Description
Summary:Logic soft-error rates are expected to exceed latch soft-error rates at advanced technology nodes due to operating frequencies in the GHz range. Predictive models for logic soft-errors need difficult-to-obtain data for single-event transient pulse widths. This work proposes an empirical method for estimating logic soft-error rates using shift registers designed with conventional D flip-flops at the 7-nm node. Availability of this model will provide insight to designers on logic soft-error contributions during the design stages.
ISSN:1938-1891
DOI:10.1109/IRPS46558.2021.9405128