Hardware Acceleration of High Sensitivity Power-Aware Epileptic Seizure Detection System Using Dynamic Partial Reconfiguration

• Published in: IEEE access 2021, Vol.9, p.75071-75081
• Main Authors: Elhosary, Heba, Zakhari, Michael H., Elgammal, Mohamed A., Kelany, Khaled A. Helal, Ghany, Mohamed A. Abd El, Salama, Khaled N., Mostafa, Hassan
• Format: Article
• Language: English
• Subjects: accelerator IP; Algorithms; Application specific integrated circuits; ASIC; classification; CMOS; Convulsions & seizures; dynamic partial reconfiguration (DPR); Feature extraction; Field programmable gate arrays; FPGA; Hardware; Integrated circuits; Low power; Machine learning; Mathematical model; Optimization; Platforms; Power consumption; Power management; Reconfiguration; Seizures; Sensitivity; sequential minimal optimization (SMO); support vector machine (SVM); Support vector machines; Technology assessment; Training
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2021.3079155

In this paper, a high-sensitivity low-cost power-aware Support Vector Machine (SVM) training and classification based system, is hardware implemented for a neural seizure detection application. The training accelerator algorithm, adopted in this work, is the sequential minimal optimization (SMO). System blocks are implemented to achieve the best trade-off between sensitivity and the consumption of area and power. The proposed seizure detection system achieves 98.38% sensitivity when tested with the implemented linear kernel classifier. The system is implemented on different platforms: such as Field Programmable Gate Array (FPGA) Xilinx Virtex-7 board and Application Specific Integrated Circuit (ASIC) using hardware-calibrated UMC 65nm CMOS technology. A power consumption evaluation is performed on both the ASIC and FPGA platforms showing that the ASIC power consumption is lower by at least 65% when compared with the FPGA counterpart. A power-aware system is implemented with FPGAs by the adoption of the Dynamic Partial Reconfiguration (DPR) technique that allows the dynamic operation of the system based on power level available to the system at the expense of degradation of the system accuracy. The proposed system exploits the advantages of DPR technology in FPGAs to switch between two proposed designs providing a decrease of 64% in power consumption.