A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS

• Published in: IEEE access 2021, Vol.9, p.77545-77554
• Main Authors: Li, Manxin, Yao, Yuting, Hu, Biao, Wei, Jipeng, Chen, Yong, Ma, Shunli, Ye, Fan, Ren, Junyan
• Format: Article
• Language: English
• Subjects: Analog to digital conversion; Analog to digital converters; asynchronous logic; Bridge circuits; Capacitors; CMOS; Control systems; Critical path; customized unit capacitor; Digital imaging; Digital to analog conversion; Digital to analog converters; figure-of-merit (FoM); Linearity; Logic arrays; Parasitic capacitance; Registers; Sampling; split-CDAC; Successive approximation register (SAR) analog-to-digital converter (ADC)
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2021.3079406

This paper presents a 12-bit 100-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for low-power wireless and imaging systems. A split-capacitor digital-to-analog converter (CDAC) structure is adopted for reducing the core area and improving the sampling speed. The linearity of the CDAC is calibrated by programming the least-significant-bits (LSBs) dummy capacitor. The unit capacitor in the CDAC array is customized for higher symmetry and reducing their mismatch. Our SAR ADC is based on asynchronous logic, and its timing is controlled by a delaying block in the critical path. The prototype is fabricated in a 65-nm CMOS process with a 1.2 V supply and occupies an active area of 0.029 mm 2 . With a 100-MS/s sampling rate, the measured ENOB scores 10.17 bits for 1.5 MHz input with a figure-of-merit (FoM) of 6.94 fJ/conversion-step. It can achieve 8.83 bits for Nyquist input signal.