A Vector Processor for Mean Field Bayesian Channel Estimation

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2021-07, Vol.29 (7), p.1348-1359
• Main Authors: Dasalukunte, Deepak, Dorrance, Richard, Liang, Le, Lu, Lu
• Format: Article
• Language: English
• Subjects: 5G NR; Algorithms; architecture; Array processors; Bayesian analysis; Bayesian inference; Channel estimation; channel estimation (CE); Hardware; Inference algorithms; Instruction sets; Machine learning; Machine learning algorithms; machine learning for signal processing; matrix co-processor; Microprocessors; Signal processing; Signal processing algorithms; Statistical inference; System on chip; vector processor; Very large scale integration; wireless; Wireless communication; Wireless communications
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2021.3077408

Physical layer signal processing algorithms in the wireless domain are seeing increased use of machine learning algorithms, especially Bayesian methods. This work presents the hardware architecture and implementation of a vector processor for one such application, Bayesian channel estimation (CE) (BCE). The BCE vector processor supports a generic instruction set with a supplement of specialized instructions to realize Bayesian algorithms in the signal processing context. The vector processor is designed to work as an accelerator in a system-on-chip (SoC) with an AHB/AXI bus interface or as stand-alone unit. The vector processor achieves more than 4\times improvement in performance when compared with a traditional CE algorithm running on a commercial vector processor. To the best of authors knowledge, this is a first known hardware implementation of a variational Bayesian inference algorithm for a wireless communication application.