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Hardware Implementation of Fixed-Point Decoder for Low-Density Lattice Codes
In this paper, a fixed-point arithmetic low-density lattice code (LDLC) decoder is designed and implemented on an FPGA where Gaussian mixture messages that are exchanged during the iterative decoding process are approximated to a single Gaussian. Numerical simulations are performed to find the minim...
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description | In this paper, a fixed-point arithmetic low-density lattice code (LDLC) decoder is designed and implemented on an FPGA where Gaussian mixture messages that are exchanged during the iterative decoding process are approximated to a single Gaussian. Numerical simulations are performed to find the minimum number of bits required for the fixed-point decoder implementation to attain a frame-error-rate (FER) performance similar to a floating-point LDLC decoder implemented in C. This is found to be 12 integer bits, 8 fractional bits and a sign bit. Efficient methods are used to numerically approximate the required non-linear functions such as division and exponentiation. A two-node serial LDLC decoder implemented on an Arria 10 FPGA is presented as a hardware proof-of-concept that attains a throughput of 440 Ksymbols/sec at high signal-to-noise ratio (SNR). This throughput is obtained at clock frequency of 125MHz and for a block length of 1000. The throughput is further improved with a partially-parallel architecture that achieves a throughput of 5.75 Msymbols/sec at high SNR. |
doi_str_mv | 10.1109/IEEECONF51394.2020.9443561 |
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The throughput is further improved with a partially-parallel architecture that achieves a throughput of 5.75 Msymbols/sec at high SNR.</description><identifier>EISSN: 2576-2303</identifier><identifier>EISBN: 9780738131245</identifier><identifier>EISBN: 0738131245</identifier><identifier>EISBN: 9780738131269</identifier><identifier>EISBN: 0738131261</identifier><identifier>DOI: 10.1109/IEEECONF51394.2020.9443561</identifier><language>eng</language><publisher>IEEE</publisher><subject>Computer architecture ; Decoding ; Field programmable gate arrays ; fixed-point arithmetic ; Gaussian mixture ; Hardware ; hardware architecture ; Lattices ; Low-density lattice code (LDLC) ; Numerical simulation ; serial and parallel FPGA architecture ; single Gaussian ; Throughput</subject><ispartof>2020 54th Asilomar Conference on Signals, Systems, and Computers, 2020, p.1295-1300</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9443561$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,27925,54555,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9443561$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Srivastava, Rachna</creatorcontrib><creatorcontrib>Gaudet, Vincent C.</creatorcontrib><creatorcontrib>Mitran, Patrick</creatorcontrib><title>Hardware Implementation of Fixed-Point Decoder for Low-Density Lattice Codes</title><title>2020 54th Asilomar Conference on Signals, Systems, and Computers</title><addtitle>IEEECONF</addtitle><description>In this paper, a fixed-point arithmetic low-density lattice code (LDLC) decoder is designed and implemented on an FPGA where Gaussian mixture messages that are exchanged during the iterative decoding process are approximated to a single Gaussian. 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The throughput is further improved with a partially-parallel architecture that achieves a throughput of 5.75 Msymbols/sec at high SNR.</description><subject>Computer architecture</subject><subject>Decoding</subject><subject>Field programmable gate arrays</subject><subject>fixed-point arithmetic</subject><subject>Gaussian mixture</subject><subject>Hardware</subject><subject>hardware architecture</subject><subject>Lattices</subject><subject>Low-density lattice code (LDLC)</subject><subject>Numerical simulation</subject><subject>serial and parallel FPGA architecture</subject><subject>single Gaussian</subject><subject>Throughput</subject><issn>2576-2303</issn><isbn>9780738131245</isbn><isbn>0738131245</isbn><isbn>9780738131269</isbn><isbn>0738131261</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2020</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotj8tqwzAURNVCoWmaL-hGdG9Xjys_lsWxE4NpumjXQZauQCW2gi1I8_c1NKtZzGE4Q8grZynnrHxr67quDh-N4rKEVDDB0hJAqozfkU2ZFyyXBZdcgLonK6HyLBGSyUfyNM8_bKFFIVak2-vJXvSEtB3OJxxwjDr6MNLgaON_0SafwY-RbtEEixN1YaJduCRbHGcfr7TTMXqDtFra-Zk8OH2acXPLNflu6q9qn3SHXVu9d4kXSsWkdCCgLKRRhQBtwC4qClD1CpXkHABYb6VwfZ5lhulCo5OWu1wLBxyVkWvy8r_rEfF4nvygp-vxdl7-AeJpTzg</recordid><startdate>20201101</startdate><enddate>20201101</enddate><creator>Srivastava, Rachna</creator><creator>Gaudet, Vincent C.</creator><creator>Mitran, Patrick</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>20201101</creationdate><title>Hardware Implementation of Fixed-Point Decoder for Low-Density Lattice Codes</title><author>Srivastava, Rachna ; Gaudet, Vincent C. ; Mitran, Patrick</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i255t-9f424983c5824ac4d02854e5b5e53114440bd32fb766c0a8aef3d1f7a2f41e5c3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2020</creationdate><topic>Computer architecture</topic><topic>Decoding</topic><topic>Field programmable gate arrays</topic><topic>fixed-point arithmetic</topic><topic>Gaussian mixture</topic><topic>Hardware</topic><topic>hardware architecture</topic><topic>Lattices</topic><topic>Low-density lattice code (LDLC)</topic><topic>Numerical simulation</topic><topic>serial and parallel FPGA architecture</topic><topic>single Gaussian</topic><topic>Throughput</topic><toplevel>online_resources</toplevel><creatorcontrib>Srivastava, Rachna</creatorcontrib><creatorcontrib>Gaudet, Vincent C.</creatorcontrib><creatorcontrib>Mitran, Patrick</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Srivastava, Rachna</au><au>Gaudet, Vincent C.</au><au>Mitran, Patrick</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Hardware Implementation of Fixed-Point Decoder for Low-Density Lattice Codes</atitle><btitle>2020 54th Asilomar Conference on Signals, Systems, and Computers</btitle><stitle>IEEECONF</stitle><date>2020-11-01</date><risdate>2020</risdate><spage>1295</spage><epage>1300</epage><pages>1295-1300</pages><eissn>2576-2303</eissn><eisbn>9780738131245</eisbn><eisbn>0738131245</eisbn><eisbn>9780738131269</eisbn><eisbn>0738131261</eisbn><abstract>In this paper, a fixed-point arithmetic low-density lattice code (LDLC) decoder is designed and implemented on an FPGA where Gaussian mixture messages that are exchanged during the iterative decoding process are approximated to a single Gaussian. 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subjects | Computer architecture Decoding Field programmable gate arrays fixed-point arithmetic Gaussian mixture Hardware hardware architecture Lattices Low-density lattice code (LDLC) Numerical simulation serial and parallel FPGA architecture single Gaussian Throughput |
title | Hardware Implementation of Fixed-Point Decoder for Low-Density Lattice Codes |
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