5 V, 300 MSa/s, 6-bit Digital Gate Driver IC for GaN Achieving 69 % Reduction of Switching Loss and 60 % Reduction of Current Overshoot

• Main Authors: Katada, Ryunosuke, Hata, Katsuhiro, Yamauchi, Yoshitaka, Wang, Ting-Wei, Morikawa, Ryuzo, Wu, Cheng-Hsuan, Sai, Toru, Chen, Po-Hung, Takamiya, Makoto
• Format: Conference Proceeding
• Language: English
• Subjects: Current measurement; digital gate driver; Field effect transistors; GaN; Integrated circuits; overshoot; Semiconductor device measurement; Simulated annealing; Switches; Switching loss
• ISSN: 1946-0201
• DOI: 10.23919/ISPSD50666.2021.9452225

A digital gate driver (DGD) is an important technology to reduce both switching loss and voltage and/or current overshoot. In this paper, a 5 V, 300 MSa/s, 6-bit DGD IC, where the gate current is varied in 64 levels for each of 16 3.3-ns time intervals, is developed using 180-nm BCD process for GaN FETs. The parameters for DGD are automatically optimized using a simulated annealing algorithm through repeated switching measurements. In the turn-on of GaN FETs at 48 V and 8 A, compared with the conventional single-step gate driving, the proposed gate drive using DGD reduces the switching loss from 3.9 μJ to 1.2 μJ by 69 % at the same the current overshoot of 3.4 A and reduces the current overshoot from 8.5 A to 3.4 A by 60 % at the same switching loss of 1.2 μJ, which clearly shows the advantage of DGD for GaN FETs.