An 85 dB DR 4 MHz BW Pipelined Noise-Shaping SAR ADC With 1-2 MASH Structure

• Published in: IEEE journal of solid-state circuits 2021-11, Vol.56 (11), p.3424-3433
• Main Authors: Oh, Sein, Oh, Younggyun, Lee, Juyong, Kim, Kihyun, Lee, Seungjun, Kim, Jintae, Chae, Hyungil
• Format: Article
• Language: English
• Subjects: Bandwidth; Counters; data converter; Energy resolution; Multi-stage noise shaping; multistage noise-shaping (MASH); Noise; noise-shaping successive approximation register (NS-SAR) ADC; Operational amplifiers; pipelined SAR ADC; Power consumption; Power demand; Power efficiency; Quantization (signal); Signal resolution; Transconductance; Transfer functions; ΔΣ analog-to-digital converter (ADC)
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2021.3086853

A pipelined noise-shaping successive approximation register (NS-SAR) ADC with 1-2 multistage noise-shaping (MASH) structure is presented. Two-stage pipelined structure consisting of 5 bit NS-SAR and 4 bit NS-SAR quantizers enables 3rd-order noise-shaping. A single operational transconductance amplifier (OTA) is shared by an integrator for noise-shaping and a residue amplifier for pipelining to maximize the power efficiency. The measured dynamic range (DR) is 84.6 dB when the sampling rate is 83.3 MS/s, bandwidth is 4 MHz, and power consumption is 3.5 mW showing Schreier figure-of-merit (FoM S,DR ) of 175.2 dB. The proposed ADC structure greatly relaxes design requirement of each SAR quantizer and can achieve high resolution and wide bandwidth with good power efficiency.