TSV-Last Integration to Replace ASIC Wire Bonds in the Assembly of X-Ray Detector Arrays

• Main Authors: Hicks, Jennifer Ovental, Malta, Dean, Bordelon, David, Richter, Daniel, Hong, Jaesub, Grindlay, Jonathan, Allen, Branden, Violette, Daniel P., Miyasaka, Hiromasa
• Format: Conference Proceeding
• Language: English
• Subjects: 3D Integration; CdZnTe; CZT; Detectors; Fabrication; Metallization; Packaging; Through-silicon via; Through-silicon vias; TSV; Wires; X-ray detector; X-ray detectors
• ISSN: 2377-5726
• DOI: 10.1109/ECTC32696.2021.00038

This paper will describe the use of through-silicon vias (TSVs) in a readout application-specific integrated circuit (ASIC) chip to replace wire bonds in the assembly of cadmium zinc telluride (CZT) X-ray detector arrays for space telescope applications. The TSV packaging approach includes solder bump connections from the back of the ASIC to the underlying board. This approach will greatly reduce the spacing between adjacent detectors in an array, eliminate potential damage to wires during assembly, and avoid any interference, which the wires can pick up during operation. We report a TSV-last integration process for the mixed signal ASIC chip used to read signals from the CZT detectors. The TSVs were integrated into existing ASIC wafers without any required redesign, and formed as blind vias from the frontside of the ASIC in metal-free areas adjacent to the wire bond pads. The TSVs were then connected to the bond pads using a routing metal layer. The wafers were bonded to temporary carriers and thinned from the backside, revealing the TSVs. After forming the redistribution lines (RDL) and under bump metallization (UBM), the wafers were released from the carriers and solder bumps were attached for subsequent assembly processes. In the sections that follow, we will review the details of the ASIC wafer post-processing, including TSV fabrication, wafer thinning, frontside and backside metallization layers, and solder bumping. We will report electrical testing of TSV daisy chains and isolation test structures. Also, results of ASIC functionality testing, performed before and after TSV insertion, will be discussed.