Chip-Last HDFO (High-Density Fan-Out) Interposer-PoP

Interposer Package-on-Package (PoP) technology was developed and has been in very high-volume production over the last several years for high-end mobile application processors (APs). This is due to its advantages of good package design flexibility, controllable package warpage at room temperature (2...

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Bibliographic Details
Main Authors: Kim, JaeYoon, Kim, KyeRyung, Lee, EunYoung, Hong, SeHwan, Kim, JiHyun, Ryu, JiYeon, Lee, JiHun, Hiner, David, Do, WonChul, Khim, JinYoung
Format: Conference Proceeding
Language:English
Subjects:
chip-last assembly manufacturing
controllable package warpage
fine copper(Cu) trace line/space and via
HDFO RDL routing layer
Interposer-PoP
Manufacturing
Production
Program processors
Routing
Semiconductor device measurement
Temperature control
Temperature measurement
ultrathin package z-height
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Summary:Interposer Package-on-Package (PoP) technology was developed and has been in very high-volume production over the last several years for high-end mobile application processors (APs). This is due to its advantages of good package design flexibility, controllable package warpage at room temperature (25°C) and high temperature (260°C), reduced assembly manufacturing cycle time and chip-last assembly manufacturing availability. To date, the laminate-substrate based interposer-PoP has been employed for high-end mobile APs with very high-volume production. Recently, this interposer-PoP design has faced some technical limitations including the need to reduce: top and bottom routing layer thickness, copper (Cu) trace line/space and via size for next generation mobile APs. These reductions may require ultra-thin package z-height and high-bandwidth bottom and top routing layers. To address these challenges, a new interposer-PoP with High-Density Fan-Out (HDFO) redistribution layer (RDL) routing layer has been designed and demonstrated. It is part of an initiative to achieve an ultra-thin package z-height, interposer-PoP structure with high bandwidth and improved signal integrity/power integrity (SI/PI) routing layer using a chip-last assembly manufacturing process flow. This paper will discuss package-level characterizations on the interposer-PoP with HDFO RDL routing layer as well as package z-height evaluation, temperature-dependent package warpage measurements and package-level reliability tests conducted in accordance with JEDEC.
ISSN:2377-5726
DOI:10.1109/ECTC32696.2021.00021