Hybrid Bonding Interconnect for Advanced Heterogeneously Integrated Processors

Die stacking enables significant performance leaps in computing capability and memory/processor integration. Conventional die stacking uses solder interconnects which suffer from several scaling limitations. A new die to die interconnect technology, hybrid bonding, removes many of these limitations...

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Bibliographic Details
Main Authors: Elsherbini, Adel, Liff, Shawna, Swan, Johanna, Jun, Kimin, Tiagaraj, Sathya, Pasdast, Gerald
Format: Conference Proceeding
Language:English
Subjects:
Conferences
Die Stacking
Die to Die Circuits
Electronic components
Fabrication
Fine Pitch Interconnect
Hybrid Bonding
Hybrid power systems
Integrated circuit interconnections
Micro-bumps
Program processors
Silicon Interposer
Stacking
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Description
Summary:Die stacking enables significant performance leaps in computing capability and memory/processor integration. Conventional die stacking uses solder interconnects which suffer from several scaling limitations. A new die to die interconnect technology, hybrid bonding, removes many of these limitations and allows several order of magnitude improvements in die-to-die connection density. In this paper, we provide an overview of hybrid bonding technology and its capabilities in the context of high-performance computing applications. The basic process & benefits of hybrid bonding vs. conventional solder interconnect are discussed. The signal integrity and power reduction benefits of hybrid bonding for several types of die-to-die interconnects are shown. We demonstrate that hybrid bonding can decrease the interconnect parasitics & correspondingly reduce the interconnect power by more than 5X. The design, manufacturing & assembly steps of our test chips and some of the fabrication results are also discussed.
ISSN:2377-5726
DOI:10.1109/ECTC32696.2021.00166