A 5-V Dynamic Class-C Paralleled Single-Stage Amplifier With Near-Zero Dead-Zone Control and Current-Redistributive Rail-to-Rail Gm-Boosting Technique

• Published in: IEEE journal of solid-state circuits 2021-12, Vol.56 (12), p.3593-3607
• Main Authors: Koh, Seok-Tae, Lee, Ji-Hun, Kang, Gyeong-Gu, Han, Hyunki, Kim, Hyun-Sik
• Format: Article
• Language: English
• Subjects: Amplifiers; Boosting; Dynamic class-C amplifier (DCCA); Logic gates; operational transconductance amplifier (OTA); output buffer; paralleled amplifier (PA); rail-to-rail (RTR); Semiconductor device measurement; slew rate (SR); Transconductance; transconductance (<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">G m)-boosting; Transient analysis; Voltage measurement
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2021.3101895

For fast buffering of large stepwise input to an nF-range capacitive load, this article presents a 5-V rail-to-rail (RTR) input-output paralleled-amplifier (PA) in which a dynamic class-C amplifier (DCCA) and a linear single-stage operational transconductance amplifier (OTA) are combined in parallel. During slew time, the DCCA, which is designed to consume a near-zero static current, dominantly supplies the dynamic current up to 8.5 mA to the output. When the output gets closer to the fine-settling region, the DCCA is rapidly faded out in virtue of a dedicated near-zero dead-zone control (NDZC), and it hands over to the linear OTA. A current-redistributive RTR G_{\text {m}} -boosting technique is also proposed so that the OTA can have a wide gain-bandwidth product (GBW) even over the RTR input range while minimizing the quiescent current dissipation. The prototype chip was fabricated only with 0.5- \mu \text{m} 5-V CMOS devices, and it occupies a die area of 0.03 \mu \text{m}^{2} . The proposed amplifier consumed a static current of 3.1 \mu \text{A} with a supply voltage of 5 V. The slew rates (SRs) with load capacitances ( C_{\mathrm {L}} ) of 0.8 and 10 nF were measured to be 10.3 and 0.86 V/ \mu \text{s} , respectively, for a step input of \Delta 4.2 V, which is a state-of-the-art result compared to prior chips. The measured GBW of 10-127 kHz was achieved over 0.8-10 nF C_{\mathrm {L}} with ≥ 59° phase margin (PM). The measured GBW deviation in a common-mode voltage ( V_{\mathrm {CM}} ) range of 0.3-4.7 V was within the maximum of 20%.