A low-power cache system for embedded processors

A low-power cache structure for embedded processors, called a cooperative cache system, is presented in this paper. The cooperative cache system reduces power consumption of the cache system by virtue of the structural characteristics that consists of two separate caches having different associativi...

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Bibliographic Details
Main Authors: Gi-Ho Park, Kil-Whan Lee, Jang-Soo Lee, Tack-Don Han, Shin-Dug Kim, Yong-Chun Kim, Seh-Woong Jeong, Kwang-Yup Lee
Format: Conference Proceeding
Language:English
Subjects:
Application specific integrated circuits
Computer science
Cooperative caching
Design engineering
Embedded computing
Energy consumption
Large scale integration
Manufacturing processes
Power engineering and energy
Power engineering computing
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Summary:A low-power cache structure for embedded processors, called a cooperative cache system, is presented in this paper. The cooperative cache system reduces power consumption of the cache system by virtue of the structural characteristics that consists of two separate caches having different associativities and block sizes. The cooperative cache system is adopted as the cache structure for the CalmRISC-32 embedded processor, the prototype chip of which was recently manufactured with a 0.25 /spl mu/m, 4-metal process by Samsung Electronics Co.
DOI:10.1109/MWSCAS.2000.951650