Hardware Trojan Classification at Gate-level Netlists based on Area and Power Machine Learning Analysis

• Main Authors: Liakos, Konstantinos G, Georgakilas, Georgios K, Plessas, Fotis C
• Format: Conference Proceeding
• Language: English
• Subjects: application specific integrated circuit; classification; Design tools; Feature extraction; gate-level netlists; Hardware; hardware trojan; industrial design tool; Logic gates; machine learning; Production; Sensitivity; Training
• ISSN: 2159-3477
• DOI: 10.1109/ISVLSI51109.2021.00081

The 21 st century has been characterized by incredible technological advancements. A key factor of this revolution is the ever-growing circuits complexity that are the core components of all electronic devices. This revolution has resulted in the development of today's computers but has also led to the creation of a new generation of device viruses, called hardware trojans (HTs). HTs can infect circuits leading to their degradation, complete destruction, or leakage of encrypted information. HTs can be inserted into any phase of the circuit production chain, they can function silently and remain undetected until triggered by a predefined mechanism to deliver their payload. In this paper, we propose a HT classification method, named hArdware Trojan Learning AnalysiS (ATLAS), that identifies HT-infected circuits using a Gradient Boosting (GB) model on data from the gate-level netlist (GLN) phase. Our method was trained on 11 GLN features extracted from 18 trojan-free (TF) and 885 trojaninfected (TI) circuits deposited in Trust-HUB using industrialgrade design tool. The performance evaluation results demonstrate that ATLAS outperforms existing algorithms in terms of Precision, Sensitivity, and F1 measures, enabling highly accurate classification between TF and TI circuits.