ASIC Power Estimation Across Revisions using Machine Learning

ASIC chip revisions often include major changes, such as new features, timing updates, and bug fixes. It is important to be able to accurately estimate dynamic and leakage power for these changes, during the architectural planning stage. Using physical design data from prior revisions, we can train...

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Bibliographic Details
Main Authors: Tariq, Ali, Yang, Howard
Format: Conference Proceeding
Language:English
Subjects:
Artificial neural networks
ASIC
Keras
Machine learning
power
Predictive models
Statistical analysis
System-on-chip
Timing
Training
XGBoost
Online Access:Request full text
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Summary:ASIC chip revisions often include major changes, such as new features, timing updates, and bug fixes. It is important to be able to accurately estimate dynamic and leakage power for these changes, during the architectural planning stage. Using physical design data from prior revisions, we can train machine learning models that can predict standard cell power within 15% to 40% of the post-route implementation for the new ASIC. We also look at multiple different machine learning frameworks to find the optimal solution for this problem.
ISSN:2164-1706
DOI:10.1109/SOCC49529.2020.9524795