Architecture and Optimization of 2T (Footprint) SRAM

• Published in: IEEE transactions on electron devices 2021-10, Vol.68 (10), p.4918-4924
• Main Authors: Chung, Chia-Che, Lin, Hsin-Cheng, Huang, Bo-Wei, Tsen, Chia-Jung, Liu, C. W.
• Format: Article
• Language: English
• Subjects: Area; Circuits; Computer architecture; FinFET; Logic gates; Metals; Microprocessors; Optimization; Random access memory; Semiconductor devices; Stability; static random access memory (SRAM); Threshold voltage; Transistors; vertical gate-all-around transistor (VFET); Wireless sensor networks; Work functions
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2021.3107474

A 6T-SRAM bitcell with the footprint of only two transistors is demonstrated by stacking four n-type vertical gate-all-around transistors (VFET) on two pFinFETs. The local interconnects are all within the footprint of the two bottom pFinFETs. The bitcell area is 0.014~\mu \text{m}^{{2}} considering the experimentally achievable metal pitch of 52 nm and bottom pFinFETs of 5 nm node. It can be further reduced to 0.009~\mu \text{m}^{{2}} considering the metal pitch of 30 nm. The minimum operating voltage is analyzed considering the dominant work function variation. The fin height of pFETs and the gate length of nFETs are used to optimize the read/write static noise margin (RSNM/WSNM) for the same bitcell area. The cell ratio is insensitive to pFET fin height and nFET gate length, leading the read stability to be less affected by pFET fin height and nFET gate length as compared to the write stability. The minimum operating voltage is reduced to 0.59 V using pFET fin height of 15 nm and nFET gate length of 20 nm to balance the read/write SNM without assist circuit techniques. The minimum operating voltage can be further improved to 0.56 V by optimizing the threshold voltage of −0.27 and 0.27 V for pFETs and nFETs, respectively. Moreover, using the negative bitline (NBL) technique can provide an additional 320 mV reduction on the write minimum operating voltage.