A high clock-offset tolerance for DSSS synchronization

A dynamic ADC sampling methodology based on error-tracking loop is proposed in this paper to improve synchronized performance in DSSS baseband transceivers. To maintain the synchronized performance the ADC sampling rate is controlled by error-tracking loop to let clock offset become lower. For 1.8 M...

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Bibliographic Details
Main Authors: Hsuan-Yu Liu, Shuenn-Der Tzeng, Yi-Chuan Liu, Chung-Cheng Wang, Terng-Ren Hsu, Terng-Yin Hsu, Chen-Yi Lee
Format: Conference Proceeding
Language:English
Subjects:
Autocorrelation
Baseband
Bit error rate
Clocks
Error correction
Frequency synchronization
Local oscillators
Sampling methods
Spread spectrum communication
Transceivers
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Summary:A dynamic ADC sampling methodology based on error-tracking loop is proposed in this paper to improve synchronized performance in DSSS baseband transceivers. To maintain the synchronized performance the ADC sampling rate is controlled by error-tracking loop to let clock offset become lower. For 1.8 MHz clock offset based on 44 MHz ADC sampling rate the BER of DSSS baseband transceivers can achieve 10/sup -5/ in AWGN channel.
DOI:10.1109/MWSCAS.2000.952909