Digital ASIC Implementation of RISC-V: OpenLane and Commercial Approaches in Comparison

Computer Aided Design (CAD) tools are widely used in Application Specific Integrated Circuit (ASIC) design. CAD tools provide a simple process for the IC design. For that purpose open source EDA tools are used for study and research of an IC design. This describes how the open source EDA tools could...

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Bibliographic Details
Main Authors: Hesham, Sarah, Shalan, Mohamed, El-Kharashi, M. Watheq, Dessouky, Mohamed
Format: Conference Proceeding
Language:English
Subjects:
Application specific integrated circuits
ASIC
CAD
Circuits and systems
Commercial tools
Design automation
EDA
IC design
Open source
OpenLane flow
Power demand
RISC-V
Timing
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Summary:Computer Aided Design (CAD) tools are widely used in Application Specific Integrated Circuit (ASIC) design. CAD tools provide a simple process for the IC design. For that purpose open source EDA tools are used for study and research of an IC design. This describes how the open source EDA tools could help the researchers and students to learn and fabricate their own Integrated circuits. In this paper, we present the digital ASIC implementation of RISC-V "DwarfRV32". The design is implemented using two approaches, which are the OpenLane flow and the Commercial tools. We then compare between the two flows on important parameters like timing performance and power consumption.
ISSN:1558-3899
DOI:10.1109/MWSCAS47672.2021.9531753