A High-performance Open-channel Open-way NAND Flash Controller Architecture

NAND-Flash-based SSDs have been widely employed in diverse computing domains and storage systems due to their higher performance and lower power consumption than HDDs. There have been various studies to explore the internal parallelism inside SSDs, including the channel-way-plane levels of interleav...

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Bibliographic Details
Main Authors: Qiu, Yunhui, Yin, Wenbo, Wang, Lingli
Format: Conference Proceeding
Language:English
Subjects:
Bandwidth
Computer architecture
Flash controller
Flash memories
FPGA
I/O Scheduling
NAND Flash
Parallelism
Power demand
Programming
Technological innovation
Topology
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Summary:NAND-Flash-based SSDs have been widely employed in diverse computing domains and storage systems due to their higher performance and lower power consumption than HDDs. There have been various studies to explore the internal parallelism inside SSDs, including the channel-way-plane levels of interleaving and the cache mode pipelining. However, most current studies are based on simulators or focus on part of the parallelism. In this paper, we present an open-source high-performance open-channel open-way NAND Flash controller supporting all the parallelism. Several architecture innovations are proposed to improve performance and resource efficiency. Firstly, the controller exposes the multi-channel, multi-way topology with a queue-based asynchronous interface for each way. Secondly, a dual-level command scheduler is integrated to enable the fine-grained way-level interleaving, plane-level interleaving, and cache mode pipelining. Finally, four finite state machines are designed for the classified Flash command groups. Evaluated on an FPGA platform, the maximum bandwidth can reach 1.2GB/s, accounting for 93% of the theoretical bandwidth, 13% higher than the bandwidth utilization of other Flash controllers. The minimum latencies for the page reading and programming are 119ps and 2ms respectively, which can be further speeded up by 1.9x and 3.1x on average with the multi-level parallelism.
ISSN:1946-1488
DOI:10.1109/FPL53798.2021.00023