Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes

For the first time, we suggested that the monolithic 3D (M3D) static random access memory (SRAM) with gate and S/D bottom contact (GBC and SDBC) schemes (SRAM SDGBC ) and analyzed they could significantly improve the power, performance, and area (PPA) compared to the conventional M3D SRAM (SRAM 3D )...

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Bibliographic Details
Published in:IEEE access 2021, Vol.9, p.138192-138199
Main Authors: Lee, Junjong, Yoon, Jun-Sik, Jeong, Jinsu, Lee, Seunghwan, Lee, Sanguk, Baek, Rock-Hyun
Format: Article
Language:English
Subjects:
3D-TCAD
6T-SRAM
Access time
FinFETs
gate bottom contact (GBC)
Interlayers
Logic gates
Metals
mixed-mode simulation
Monolithic 3D (M3D)
Performance evaluation
power performance and area (PPA)
Random access memory
Resistance
source/drain bottom contact (SDBC)
Static random access memory
Three-dimensional displays
Transistors
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Summary:For the first time, we suggested that the monolithic 3D (M3D) static random access memory (SRAM) with gate and S/D bottom contact (GBC and SDBC) schemes (SRAM SDGBC ) and analyzed they could significantly improve the power, performance, and area (PPA) compared to the conventional M3D SRAM (SRAM 3D ). SRAM 3D could not directly connect the top-tier device and the bottom-tier metal line. Thus two tiers had to be connected by bypassing the metal line. As a result, SRAM 3D wasted the area to place the monolithic interlayer via and did not get 50 % area scaling. However, gate and S/D bottom contact schemes, GBC and SDBC, could solve these problems. Although these methods required additional process steps, they brought significant advantages in interconnect RC and PPA. Based on a 26 nm width nanosheet transistor, SRAM 3D showed a 30 % area reduction compared to 2D SRAM (SRAM 2D ), whereas SRAM SDGBC showed a 50 % area reduction. In the ideal (worst) case which ignoring (considering) the array resistance, the read and write access time of SRAM SDGBC were improved 7.7 % (19 %) and 8.3 % (33 %) than SRAM 3D , and the write dynamic power was improved by 5.9 % (5 %). Especially, SRAM SDGBC showed improved PPA in the worst case compared to SRAM 2D_Cu , which had relatively small interconnect resistivity. Namely, GBC and SDBC schemes are essential to enhance the PPA of M3D cells and will be a promising scheme in M3D SRAM and other logic cells.
ISSN:2169-3536
2169-3536
DOI:10.1109/ACCESS.2021.3117719