Delay/slope budgeting for clock buffer cell design

This paper presents a delay/slope budgeting method for clock buffers design in the standard cell library. The key idea is to include the skew estimation during the budgeting process. Within-die random variations such as the polyCD WL process, temperature and supply voltage are considered in the skew...

Full description

Saved in:
Bibliographic Details
Main Authors: Zhu, Q.K., Chan, T.W.
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
Clocks
Delay
Integrated circuit modeling
Libraries
Microprocessors
MOSFETs
Semiconductor device measurement
Temperature
Voltage
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper presents a delay/slope budgeting method for clock buffers design in the standard cell library. The key idea is to include the skew estimation during the budgeting process. Within-die random variations such as the polyCD WL process, temperature and supply voltage are considered in the skew simulation for a 0.13 /spl mu/m process.
DOI:10.1109/ICECS.2001.957768