QuCTS-Single-Flux Quantum Clock Tree Synthesis

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 2022-10, Vol.41 (10), p.3346-3358
• Main Authors: Bairamkulov, Rassul, Jabbari, Tahereh, Friedman, Eby G.
• Format: Article
• Language: English
• Subjects: Circuits; Clocks; CMOS; Delays; Fanout; Gates (circuits); Integrated circuit interconnections; Integrated circuits; Logic circuits; Logic gates; Network design; Power consumption; Registers; Robustness; Sequential circuits; Superconductors; Synthesis; Transmission lines
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2021.3123141

Superconductive rapid single-flux quantum (RSFQ) is an emerging cryogenic technology, promising a significant boost in performance and ultralow power consumption. The operating frequency achieved by RSFQ digital integrated circuits is several orders of magnitude greater than traditional CMOS circuits. The fundamental difference of RSFQ circuits, however, renders traditional clocking techniques appropriate for CMOS unsuitable for RSFQ technology. Most RSFQ logic gates, such as AND and OR, are sequential in nature. The number of pipeline stages is therefore significantly greater in RSFQ as compared to CMOS, complicating the clock distribution network design process. This issue is further exacerbated with the need for splitters to achieve a fanout greater than one and the need for transmission lines rather than ordinary metallic wires as in CMOS. In this work, QuCTS-single-flux Quantum (SFQ) Clock Tree Synthesis-is presented. QuCTS utilizes a two-stage framework for synthesizing clock networks. In the clock skew scheduling stage, the clock signal arrival time of each gate is chosen to maximize the robustness of the circuit to timing variations. In the clock tree synthesis stage, the layout of the clock distribution network is generated based on a novel delay equilibration technique. QuCTS is the first clock tree synthesis tool for RSFQ circuits utilizing useful clock skew. The synthesized network satisfies the clock arrival time requirements while minimizing the associated overhead, such as the interconnect length and number of delay elements. The tool is validated on a set of benchmark circuits. In a prototypical case study, a clock tree is generated for the AMD2901 with 1049 clock sinks in 53 min while satisfying the clock arrival time.