A High-Level Approach for Energy Efficiency Improvement of FPGAs by Voltage Trimming

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 2022-10, Vol.41 (10), p.3548-3552
• Main Authors: Safarpour, Mehdi, Xun, Lei, Merrett, Geoff V., Silven, Olli
• Format: Article
• Language: English
• Subjects: Calibration; Clocks; Deep neural networks; Delays; Electric potential; Energy dissipation; Error detection; Field programmable gate arrays; Hardware; High level synthesis; high-level synthesis (HLS); Logic circuits; low power; low voltage; Matrices (mathematics); matrix multiplier; Multilayers; Neural networks; Power efficiency; System on chip; Voltage; Voltage control
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2021.3127153

Chip manufacturers define voltage margins on top of the "best-case" operational voltage of their chips to ensure reliable functioning in the worst-case settings. The margins guarantee correctness of operation, but at the cost of performance and power efficiency. Violating the margins is tempting to save energy, but might lead to timing errors. This article proposes an algorithmic solution that enables reliable removal of the margins by detecting errors on the fly. In contrast to previous approaches that require special hardware to detect timing errors, the proposed method is fully implementable using high-level synthesis tools without reliance on additional hardware. The approach is demonstrated using a 32 \times 32 matrix-matrix multiplication and a simple multilayer neural network implemented on two Xilinx ZC702 field-programmable gate array (FPGA) System-on-Chip (SoC) platforms, showcasing its utility in detecting errors that may originate from different sources of logic circuits, clock tree, or memory. Results show that the energy dissipation is halved, while the implementation is clocked at 2.5x faster than specified by the design tool of the vendor.