A 208-GHz Injection Locking Doubler Chain With 3.2% PAE and 2.9-mW Output Power in CMOS Technology

• Published in: IEEE microwave and wireless components letters 2022-04, Vol.32 (4), p.351-354
• Main Authors: Peng, Zhigang, Chen, Jingjun, Wang, Hao, Zhang, Li, Hong, Wei, Liu, Xiaoguang
• Format: Article
• Language: English
• Subjects: <italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">G -band; Chains; CMOS; frequency doubler; Frequency locking; Frequency ranges; Harmonic analysis; harmonic reflector; High gain; injection locking; Injection-locked oscillators; Logic gates; Oscillators; Power consumption; Power generation; subterahertz (sub-THz); Topology; Transformers; Transistors
• ISSN: 1531-1309; 2771-957X; 1558-1764; 2771-9588
• DOI: 10.1109/LMWC.2021.3129545

This letter presents an injection locking doubler chain centered at 208 GHz in 65-nm CMOS technology. The doubler chain consists of a doubler and two injection locking oscillators (ILOs). The doubler uses push-push topology to generate wideband second-harmonic output. Both ILOs are based on T-embedding network oscillator for high gain and high efficiency. The measured injection locking range is 188.4-225.6 GHz with the input injection power less than 0 dBm. The peak output power with the minimum injection input is 4.6 dBm (2.9 mW), and the 3-dB bandwidth is 200-220 GHz (9.5%). The power consumption is 83 mW under 1.2-V supply, and the peak power-added efficiency (PAE) reaches 3.2% at 211 GHz. Moreover, the total size of the chip excluding pads is 530 \mu \text{m}\,\,\times200\,\,\mu \text{m} . To the best of the author's knowledge, this work demonstrates the highest PAE among CMOS doubler chains in similar frequency ranges reported by far.