A technique for fault diagnosis of defects in scan chains

• Main Authors: Ruifeng Guo, Venkataraman, S.
• Format: Conference Proceeding
• Language: English
• Subjects: Automatic test pattern generation; Circuit faults; Circuit testing; Failure analysis; Fault diagnosis; Flip-flops; Logic circuits; Logic design; Test pattern generators; Timing
• ISSN: 1089-3539; 2378-2250
• DOI: 10.1109/TEST.2001.966642

In this paper, we present a scan chain fault diagnosis procedure. The diagnosis for a single scan chain fault is performed in three steps. The first step uses special chain test patterns to determine both the faulty chain and the fault type in the faulty chain. The second step uses a novel procedure to generate special test patterns to identify the suspect scan cell within a range of scan cells. Unlike previously proposed methods that restrict the location of the faulty scan cell only from the scan chain output side, our method restricts the location of the faulty scan cell from both the scan chain output side and the scan chain input side. Hence the number of suspect scan cells is reduced significantly in this step. The final step further improves the diagnostic resolution by ranking the suspect scan cells inside this range. The proposed technique handles both stuck-at and timing failures (transition faults and hold time faults). The extension of the procedure to diagnose multiple faults is discussed. The experimental results show the effectiveness of the proposed method.