Design and Implementation of RS(1023,847) Parallel Decoder

Aiming at the realization and performance improvement of RS decoder parallelization in 25G passive optical network, this paper proposes an RS (1023, 847) parallel decoder with 880bit error correction capability based on IEEE 802.3av standard and 10G/100G Ethernet PCS layer specification. Firstly, th...

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Bibliographic Details
Main Authors: Hui, Yingzhao, Zhang, Liguo, Ma, Jiahui, Tan, Jingxuan, Li, Xingjin, Wei, Yuanyuan
Format: Conference Proceeding
Language:English
Subjects:
Automation
Chien Search and Forney Algorithm
Encoding
EPON
Euclidean Algorithm
Forward error correction
IEEE 802.3 Standard
Mechatronics
Parallel RS Decoder
Syndrome Polynomial
Throughput
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Summary:Aiming at the realization and performance improvement of RS decoder parallelization in 25G passive optical network, this paper proposes an RS (1023, 847) parallel decoder with 880bit error correction capability based on IEEE 802.3av standard and 10G/100G Ethernet PCS layer specification. Firstly, the basic principle of RS decoding algorithm is analyzed, and the corresponding syndrome polynomial module, Euclidean algorithm module and error mode calculation module are designed according to the parallel requirements of decoder. Secondly, RS (1023, 847) parallel decoder is implemented and analyzed. The results show that the proposed RS (1023, 847 ) parallel decoder has a working frequency of 454Mhz, error correction capability of 880bit, encoding gain of 8dB and throughput of 31.78Gbps. The circuit resource is 25518ALMS, and the above results all meet the working requirements of FEC circuit in PCS layer of 25G passive optical network.
ISSN:2157-1481
DOI:10.1109/ICMTMA54903.2022.00182