A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface

• Main Authors: Yuh, Jong, Li, Jason, Li, Heguang, Oyama, Yoshihiro, Hsu, Cynthia, Anantula, Pradeep, Jeong, Stanley, Amarnath, Anirudh, Darne, Siddhesh, Bhatia, Sneha, Tang, Tianyu, Arya, Aditya, Rastogi, Naman, Ookuma, Naoki, Mizukoshi, Hiroyuki, Yap, Alex, Wang, Demin, Kim, Steve, Wu, Yonggang, Peng, Min, Lu, Jason, Ip, Tommy, Malhotra, Seema, Han, David, Okumura, Masatoshi, Liu, Jiwen, Sohn, John, Chibvongodze, Hardwell, Balaga, Muralikrishna, Matsuda, Aki, Puri, Chakshu, Chen, Chen, V, Indra K, G, Chaitanya, Ramachandra, Venky, Kato, Yosuke, Kumar, Ravi, Wang, Huijuan, Moogat, Farookh, Yoon, In-Soo, Kanda, Kazushige, Shimizu, Takahiro, Shibata, Noboru, Shigeoka, Takashi, Yanagidaira, Kosuke, Kodama, Takuyo, Fukuda, Ryo, Hirashima, Yasuhiro, Abe, Mitsuhiro
• Format: Conference Proceeding
• Language: English
• Subjects: Conferences; Discrete Fourier transforms; Programming; Stairs; System performance; Three-dimensional displays; Throughput
• ISSN: 2376-8606
• DOI: 10.1109/ISSCC42614.2022.9731110

The presented 1Tb 4b/cell 162 WL layer 3D Flash memory achieves an areal density of 15 Gb/mm 2 which is 8.7% higher than prior work [1]. High-performance is the key enabler for 4b/cell NAND Flash to enter mainstream systems. This work delivers a 60MB/s programming throughput and a 65μs t R with an 8kB central WL stair architecture and contact-through-WL (CTW) region. 2.4Gb/s I/O speed is achieved with LTT and CTT combo drivers. A 45% reduction in the read and write data transfer energy is achieved by employing V CCQ domain design. A time-division peak-power-management (TD-PPM) feature effectively reduces system peak power while maximizing system performance. Cache DFT and I/O DFT functions enable a high-speed testing methodology at wafer level. These features are summarized and compared to previously reported 4b/cell Flash memories in Fig. 7.1.1.